In the conventional semiconductor packages, leadframes have been widely implemented as chip carriers and as electrical connection media. There are several basic packaging configurations according to the features of the chip carriers such as Chip-On-Lead packages (COL), Lead-On-Chip (LOC) packages, and conventional “chip on die pad” packages where COL packages are to attach the back surfaces of the chips, i.e., the surfaces of the chips without ICs, to certain internal sections of the leads, then the chips and the leads of leadframes are encapsulated by molding. In order to balance the upper and lower mold flows during transfer molding, at least two downset bends are formed on the leads or on the tie bars of the die pad leading to shaking of the leads. Once experienced the pressure of the mold flows during molding processes, the leads having downset bends are sensitive to shift or deform, therefore, space should be reserved in the encapsulant to prevent the internal packaging components such as chips or leads from atmosphere exposure and contaminations. Hence, the number of chips can be stacked inside a package is limited, especially the structural strengths of the leads of COL packages are not strong enough to hold and stack the chips leading to shifting and tilting. Once the chip position changes, the upper and lower mold flows cannot be balanced.
As shown in FIG. 1, a conventional COL multi-chip package 100 comprises a plurality of first leads 110, a plurality of second leads 120, a first chip 130, a second chip 140, and an encapsulant 150. The first leads 110 and the second leads 120 are made of the same leadframe and are inwardly extended from two opposing sides of the encapsulant 150. The first leads 110 have a plurality of first internal leads 111 and a plurality of first external leads 112. The second leads 120 have a plurality of second internal leads 121 and a plurality of second external leads 122. The lengths of the first internal leads 111 are greater than the ones of the second internal leads 122 to support the first chip 130 and the second chip 140 attached thereon. The first external leads 112 and the second external leads 122 extend from the sides of the encapsulant 150 and are bent to a specific shape such as gull leads for external electrical connections. As shown in FIG. 1 again, each internal lead 111 has a first downset bend 114 and a second downset bend 115 formed in the encapsulant 150 to make the chip-attached portions of the first internal leads 111 in a downset position. The first chip 130 has a plurality of first bonding pads 133 on its active surface. The back surface of the chip 130 is disposed on the chip-attached portions of the first internal leads 111. The first bonding pads 133 are electrically connected to the first internal leads 111 and the second internal leads 121 by a plurality of first bonding wires 160. The second chip 140 has a plurality of second bonding pads 143 and is back-to-face stacked on the first chip 130. The second bonding pads 143 are electrically connected to the first internal leads 111 and the second internal leads 121 by a plurality of second bonding wires 170. The encapsulant 150 encapsulates the first internal leads 111, the second internal leads 121, the first chip 130, the second chip 140, the first bonding wires 160, and the second bonding wires 170 with the first external leads 112 and the second external leads 122 exposed. As shown in FIG. 1 again, since the first internal leads 111 experienced two downset bending, i.e., the first downset bend 114 and the second downset bend 115 to change vertical locations of the chips 130 and 140, therefore, the structural strengths of the first internal leads 111 are reduced and the horizontal plane of the first internal leads 111 cannot be firmly controlled. Hence, the first internal leads 111 will shift or tilt due to the pressure of the mold flows during transfer molding leading to the first internal leads 111, the second chip 140, or the bonding wires 170 exposed from the encapsulant 150. Furthermore, the mold flow will further pull the first bonding wires 160 and the second bonding wires 170 leading to broken wires, electrical shorts and lower package yield. Moreover, in order to avoid the second chip 140 to contact the first bonding wires 160 of the first chip 130 stacked below, an interposer 190 such as a dummy chip or PI tape is disposed between the first chip 130 and the second chip 140, however, the stackable heights of the chips are reduced, therefore, more chips can not be stacked. Since the peripheries of the second chip 140 without contacting with the attached portion of the interposer 190 including the peripheries for bonding the second bonding wires 143 can not be supported by the interposer 190 and become overhang during wire bonding. In order to get better wile bonding support for the second bonding wires 170, a certain thickness of the second chip 140 is required which further limits the number of chips can be stacked in the package 100.